Method and apparatus for circuit breaker node software architecture

ABSTRACT

A method and apparatus for operating a centrally controlled power distribution system is provided. The power distribution system includes a plurality of circuit breakers, each circuit breaker coupled to a single node electronics unit, the node electronics unit includes a plurality of processors and a memory, and the node electronics unit is communicatively coupled to at least one central control processing unit through an associated network. The method includes triggering a first node electronics unit process with a processor interrupt, and triggering a second node electronics unit process with at least one of a background polling of process execution flags and scheduled processor interrupts. The apparatus includes a software program code segment configured to trigger a first node electronics unit process with a processor interrupt, and trigger a second node electronics unit process with at least one of a background polling of process execution flags and scheduled processor interrupts.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is related to U.S. Patent Application No.60/359,544 filed on Feb. 25, 2002 for “Integrated Protection,Monitoring, and Control” the content of which is incorporated in itsentirety herein by reference. This application is also related to U.S.Patent Application No. 60/438,159 filed on Jan. 6, 2003 for “SingleProcessor Concept for Protection and Control of Circuit Breakers inLow-Voltage Switchgear” the content of which is incorporated in itsentirety herein by reference.

BACKGROUND OF THE INVENTION

[0002] This invention relates generally to electrical switchgear andmore particularly, to a method and apparatus for operating a centrallycontrolled power distribution system circuit breaker node electronicsunit.

[0003] In an industrial power distribution system, power generated by apower generation company may be supplied to an industrial or commercialfacility wherein the power may be distributed throughout the industrialor commercial facility to various equipment such as, for example,motors, welding machinery, computers, heaters, lighting, and otherelectrical equipment. At least some known power distribution systemsinclude switchgear which facilitates dividing the power into branchcircuits which supply power to various portions of the industrialfacility. Circuit breakers are provided in each branch circuit tofacilitate protecting equipment within the branch circuit. Additionally,circuit breakers in each branch circuit can facilitate minimizingequipment failures since specific loads may be energized or de-energizedwithout affecting other loads, thus creating increased efficiencies, andreduced operating and manufacturing costs. Similar switchgear may alsobe used within an electric utility transmission system and a pluralityof distribution substations, although the switching operations used maybe more complex.

[0004] Switchgear typically include multiple devices, other than thepower distribution system components, to facilitate providingprotection, monitoring, and control of the power distribution systemcomponents. For example, at least some known breakers include aplurality of shunt trip circuits, under-voltage relays, trip units, anda plurality of auxiliary switches that close the breaker in the event ofan undesired interruption or fluctuation in the power supplied to thepower distribution components. Additionally, at least one known powerdistribution system also includes a monitor device that monitors aperformance of the power distribution system, a control device thatcontrols an operation of the power distribution system, and a protectiondevice that initiates a protective response when the protection deviceis activated.

[0005] In at least some other known power distribution systems, amonitor and control system operates independently of the protectivesystem. For example, a protective device may de-energize a portion ofthe power distribution system based on its own predetermined operatinglimits, without the monitoring devices recording the event. The failureof the monitoring system to record the system shutdown may mislead anoperator to believe that an over-current condition has not occurredwithin the power distribution system, and as such, a proper correctiveaction may not be initiated by the operator. Additionally, a protectivedevice, i.e. a circuit breaker, may open because of an over-currentcondition in the power distribution system, but the control system mayinterpret the over-current condition as a loss of power from the powersource, rather than a fault condition. As such, the control logic mayundesirably attempt to connect the faulted circuit to an alternatesource, thereby restoring the over-current condition. In addition to thepotential increase in operational defects which may occur using suchdevices, the use of multiple devices and interconnecting wiringassociated with the devices may cause an increase in equipment size, anincrease in the complexity of wiring the devices, and/or an increase ina quantity of devices installed.

BRIEF DESCRIPTION OF THE INVENTION

[0006] In one aspect, method for operating a centrally controlled powerdistribution system is provided. The power distribution system includesa plurality of circuit breakers, each circuit breaker coupled to asingle node electronics unit, the node electronics unit includes aplurality of processors and a memory, and the node electronics unit iscommunicatively coupled to at least one central control processing unitthrough an associated network. The method includes triggering a firstnode electronics unit process with a processor interrupt, and triggeringa second node electronics unit process with at least one of a backgroundpolling of a plurality of process execution flags and a scheduledprocessor interrupt.

[0007] In another aspect, apparatus for operating a centrally controlledpower distribution system is provided. The power distribution systemincludes a plurality of circuit breakers, each circuit breaker coupledto a single node electronics unit, said node electronics unit includes aprocessor and a memory, and the node electronics unit is communicativelycoupled to at least one central control processing unit through anassociated network. The apparatus includes a software program codesegment configured to trigger a first node electronics unit process witha processor interrupt, trigger a second node electronics unit processwith at least one of a background polling of a plurality of processexecution flags and a scheduled processor interrupt.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is an exemplary schematic illustration of a powerdistribution system;

[0009]FIG. 2 is an exemplary schematic illustration of a node powersystem;

[0010]FIG. 3 is an exemplary schematic illustration of a central controlprocessing unit that may used with the power distribution system shownin FIG. 1;

[0011]FIG. 4 is an exemplary schematic illustration of a node electronicunit that may used with the power distribution system shown in FIG. 1;

[0012]FIG. 5 is an exemplary schematic illustration of a circuit breakerthat may used with the power distribution system shown in FIG. 1; and

[0013]FIG. 6 is an expanded schematic block diagram of an exemplary nodeelectronics unit shown in FIG. 4.

[0014]FIG. 7 is a flow chart illustrating an exemplary method foroperating the node electronics unit shown in FIG. 6.

DETAILED DESCRIPTION OF THE INVENTION

[0015]FIG. 1 illustrates an exemplary schematic illustration of a powerdistribution system 10, used by an industrial facility for example. Inan exemplary embodiment, system 10 includes at least one main feedsystem 12, a power distribution bus 14, a plurality of power circuitswitches or interrupters, also referred to herein as a circuit breakers(CB) 16, and at least one load 18, such as, but not limited to, motors,welding machinery, computers, heaters, lighting, and/or other electricalequipment.

[0016] In use, power is supplied to a main feed system 12, i.e. aswitchboard for example, from a source (not shown) such as, an electricgenerator driven by a prime mover locally, or an electric utility sourcefrom an electrical substation. The prime mover may be powered from, forexample, but not limited to, a turbine, or an internal combustionengine. Power supplied to main feed system 12 is divided into aplurality of branch circuits by a plurality of busbars configured toroute the power from a branch feed breaker and a bus-tie breaker to aplurality of load circuit breakers 16 which supply power to variousloads 18 in the industrial facility. In addition, circuit breakers 16are provided in each branch circuit to facilitate protecting equipment,i.e. loads 18, connected within the respective branch circuit.Additionally, circuit breakers 16 facilitate minimizing equipmentfailures since specific loads 18 may be energized or de-energizedwithout affecting other loads 18, thus creating increased efficiencies,and reduced operating and manufacturing costs.

[0017] Power distribution system 10 includes a circuit breaker controlprotection system 19 that includes a plurality of node electronics units20 that are each communicatively coupled to a digital network 22 via anetwork interface controller switch 23 such as, but not limited to, anEthernet switch 23. Circuit breaker control protection system 19 alsoincludes at least one central control processing unit (CCPU) 24 that iscommunicatively coupled to digital network 22. In use, each respectivenode electronic unit 20 is electrically coupled to a respective circuitbreaker 16, such that CCPU 24 is communicatively coupled to each circuitbreaker 16 through digital network 22 and through an associated nodeelectronic unit 20.

[0018] In one embodiment, digital network 22 includes, for example, atleast one of a local area network (LAN) or a wide area network (WAN),dial-in-connections, cable modems, and special high-speed ISDN lines.Digital network 22 also includes any device capable of interconnectingto the Internet including a web-based phone, personal digital assistant(PDA), or other web-based connectable equipment.

[0019] In one embodiment, CCPU 24 is a computer and includes a device26, for example, a floppy disk drive or CD-ROM drive, to facilitatereading instructions and/or data from a computer-readable medium 28,such as a floppy disk or CD-ROM. In another embodiment, CCPU 24 executesinstructions stored in firmware (not shown). CCPU 24 is programmed toperform functions described herein, but other programmable circuits canlikewise be programmed. Accordingly, as used herein, the term computeris not limited to just those integrated circuits referred to in the artas computers, but broadly refers to computers, processors,microcontrollers, microcomputers, programmable logic controllers,application specific integrated circuits, and other programmablecircuits. Additionally, although described in a power distributionsetting, it is contemplated that the benefits of the invention accrue toall electrical distribution systems including industrial systems suchas, for example, but not limited to, an electrical distribution systeminstalled in an office building.

[0020]FIG. 2 is an exemplary schematic illustration of a node powerdistribution system 29 that can be used with power distribution system10 (shown in FIG. 1) and more specifically, with circuit breaker controlprotection system 19 (shown in FIG. 1). Node power distribution system29 includes a power source 30 that is electrically coupled to nodeelectronic units 20 through a node power distribution bus 32. In anexemplary embodiment, power source 30 is an uninterruptible power supply(UPS). In one embodiment, power source 30 receives power from powersystem 10 and then distributes this power to node electronic units 20through node power distribution bus 32. In an alternative embodiment,power is not supplied to power source 30, but rather, power source 30supplies power to node electronic units 20 using an internal powersupply, such as, but not limited to, a plurality of batteries (notshown). In another alternate embodiment, node electronic units 20 arepowered by secondary current available from current sensor 82 and/orvoltage sensor 84. In this embodiment, circuit breaker controlprotection system 19 would not include node power distribution system29, power source 30, or node power distribution bus 32.

[0021]FIG. 3 is an exemplary schematic illustration of CCPU 24. CCPU 24includes at least one memory device 40, such as, but not limited to, aread only memory (ROM) 42, a flash memory 44, and/or a random accessmemory (RAM) 46. CCPU 24 also includes a central processor unit (CPU) 48that is electrically coupled to at least one memory device 40, as wellas an internal bus 50, a communications interface 52, and acommunications processor 54. In an exemplary embodiment, CCPU 24 is aprinted circuit board and includes a power supply 56 to supply power toa plurality of devices on the printed circuit board.

[0022] Additionally, in an exemplary embodiment, internal bus 50includes an address bus, a data bus, and a control bus. In use, theaddress bus is configured to enable CPU 48 to address a plurality ofinternal memory locations or an input/output port, such as, but notlimited to communications interface 52 through communications processor54, and a gateway interface 57, through a gateway processor 58. The databus is configured to transmit instructions and/or data between CPU 48and at least one input/output, and the control bus is configured totransmit signals between the plurality of devices to facilitate ensuringthat the devices are operating in synchronization. In the exemplaryembodiment, internal bus 50 is a bidirectional bus such that signals canbe transmitted in either direction on internal bus 50. CCPU 24 alsoincludes at least one storage device 60 configured to store a pluralityof information transmitted via internal bus 50.

[0023] In use, gateway interface 57 communicates to a remote workstation(not shown) via an Internet link 62 or an Intranet 62. In the exemplaryembodiment, the remote workstation is a personal computer including aweb browser. Although a single workstation is described, such functionsas described herein can be performed at one of many personal computerscoupled to gateway interface 57. For example, gateway interface 57 maybe communicatively coupled to various individuals, including localoperators and to third parties, e.g., remote system operators via an ISPInternet connection. The communication in the example embodiment isillustrated as being performed via the Internet, however, any other widearea network (WAN) type communication can be utilized in otherembodiments, i.e., the systems and processes are not limited to beingpracticed via the Internet. In one embodiment, information is receivedat gateway interface 57 and transmitted to node electronic unit 20 viaCCPU 24 and digital network 22. In another embodiment, information sentfrom node electronic unit 20 is received at communication interface 52and transmitted to Internet 62 via gateway interface 57.

[0024]FIG. 4 is an exemplary schematic block diagram of single nodeelectronics unit 20. In the exemplary embodiment, node electronics unit20 is a unitary device mounted remotely from CCPU 24 and breaker 16. Forexample, node electronics unit 20 can be separate from, but proximate tocircuit breaker 16. Node electronics unit 20 includes a communicationsinterface 70 that is coupled to digital network 22. In the exemplaryembodiment, communication interface 70 communicates over network 22using Fast Ethernet protocol at about 100 Mbps. In another embodiment,node electronics unit 20 includes a plurality of communicationinterfaces 70 that couple to an equal number of independent networks 22which, in turn, each couple to independent CCPUs 24. Such anarchitecture provides a redundancy that facilitates operation of powerdistribution system 10. A number of independent, redundantcommunications interfaces 70, networks 22 and CCPUs 24 is determined bya predetermined redundancy requirement of a user. Each communicationinterface 70 couples electrically to a node processor 72 to transmitdata received from a respective CCPU 24 to node processor 72 and totransmit data received from node processor 72 to respective CCPU 24. Inan alternative embodiment, node electronics units 20 include a pluralityof node processors 72. At least one of the plurality of node processors72 may comprise a self-powered processor. A self-powered processorreceives power from a self-power supply circuit 73. In an embodimentwherein a self-powered processor is used, the self-powered processor isconfigured to conserve electrical energy when power supply 80 is unableto supply the electrical requirements of the node electronics units 20.It should be appreciated that, in one embodiment, the self-poweredprocessor conserves energy by being configured to execute onlypredetermined processes such that the self powered-processor conservesenergy. In such a case, self-powered processor is configured for fastwakeup, i.e. an abbreviated initialization process when first powered.It should be further appreciated that, in another embodiment, the fastwakeup configuration allows the self-powered processor to conserveenergy by executing only predetermined processes. Self-powered processoris additionally configured to modify its clock speed and processing tocoordinate its power usage with power available through self-powersupply circuit and power supply 80. Node processor 72 includes a memory,a communication processor and a command interpreter within. The clocksof each node processor 72 in the plurality of node electronics units 20in power distribution system 10 are synchronized by a synchronizationpulse received from at least one CCPU 24. Node electronics units 20determines which synchronization signal received synchronizes the nodeprocessors 72.

[0025] Node processor 72 is electrically coupled to a memory device 74,such as, but not limited to a flash memory device, an analog digital(A/D) converter 76, and a signal conditioner 78. Node processor 72 iscommunicatively coupled to communications interface 70. Memory device 74is also communicatively coupled to node processor 72 for exchangingdata, and program instructions. In one embodiment, memory device 74 is asingle device including a program area and a data area. In analternative embodiment, memory 74 is a plurality of devices, eachincluding an area for a program, data and configuration constantinformation. In an embodiment wherein a plurality of node processors 72are used, memory 74 includes a separate device dedicated to each nodeprocessor 72 and a shared memory area accessible and modifiable by eachnode processor 72. Node processor 72 is electrically coupled to A/Dconverter 76 to receive digital signals representing analog signalsreceived from signal conditioner 78. Analog signals from sensors locatedremotely from circuit breaker 16 and node electronics unit 20 monitorelectrical parameters associated with respective circuit breaker 16. Theanalog signals are received by signal conditioner 78 from CT input 82and PT input 84. CT input 82 is electrically coupled to an input CT anda burden resistor (not shown). Input current flowing through the burdenresistor induces a voltage drop across the burden resistor that isproportional to the input current. The induced voltage is sensed atsignal conditioner 78 input. Signal conditioner 78 includes a filteringcircuit to improve a signal to noise ratio of the incoming signal, again circuit to amplify the incoming signal, a level adjustment circuitto shift the incoming signal to a pre-determined range, and an impedancematch circuit to facilitate a signal transfer to A/D converter 76. Inthe exemplary embodiment, A/D converter 76 is a sample and hold type ofA/D converter. The sample and hold feature facilitates synchronizationof electrical parameter measurements in node electronics units 20. A/Dconverter 76 samples signal conditioner 78 output when commanded by nodeprocessor 72, which issues synchronization commands as directed by CCPU24. In an exemplary embodiment, node electronics unit 20 is a printedcircuit board and includes a power supply 80 to power a plurality ofdevices on the printed circuit board.

[0026] In one embodiment, node electronics unit 20 receives signalsinput from a plurality of devices, such as, but not limited to, acurrent transformer 82, and a potential transformer 84, and/or a circuitbreaker 16. A plurality of inputs from the circuit breaker 16 areprovided as status input 86, and these inputs may include inputs, suchas, but not limited to, an auxiliary switch status, and a spring chargeswitch status. In one embodiment, current transformer 82 includes aplurality of current transformers, each monitoring a different phase ofa three phase power system, and at least one current transformermonitoring a neutral phase of the three phase power system. In anotherembodiment, potential transformer 84 includes a plurality of potentialtransformers, each monitoring a different phase of a three-phase powersystem. An actuation relay module 88 is communicatively coupled to nodeprocessor 72 and module 88 is also coupled to an actuation power module90. Status input module and actuation power module 90 are electricallycoupled to circuit breaker 16 through a standard wiring harness.

[0027] In one embodiment, node electronics unit 20 includes a secondnode processor 72 that executes a program code segment that determineslocal control and protection actions to be used to determine breakercommands when communications between node electronics unit 20 and CCPU24 is lost. The second node processor is powered from an electricalsource onboard the node electronics unit separate and independent fromthe control system power supply that supplies the other components ofnode electronics unit 20. In this embodiment, first node processor 72 isconfigured to execute a program code segment that controls all otherfunctions of nod electronics unit 20, including, but, not limited to,communications functions performed by communications interface 70, inputfunctions performed by signal conditioner 78, A/D 76, and status input86, and output functions performed by actuation relay 88 and actuationpower module 90. Second node processor 72 includes a memory separate andindependent from memory unit 74.

[0028] In use, the status inputs 86 and signals received from currenttransformer 82, and potential transformer 84, are conditioned by signalconditioner 78 and transmitted to A/D converter 76, where the analogsignals are converted to digital signals for input to node processor 72.Node processor 72 executes software that is resident on memory 74. Thesoftware instructs node processor 72 to receive digital signals from A/Dconverter 76 and logical status signals from circuit breaker 16 throughstatus input 86. Node processor 72 compares the input signals toparameters determined by software executing on node processor 72 andparameters in control and protective actions received from CCPU 24through network 22 and communications interface 70. Node processor 72determines local control and protective actions based on the inputsignals and the control and protective actions received from CCPU 24. Ifnode processor 72 and CCPU are communicating properly, a local blocksignal received from CCPU 24 inhibits node processor 72 from using thelocal control and protective actions from determining a set of breakercontrol actions. The breaker control actions are a set of signals thatcommand circuit breaker 16 to operate in a predetermined manner. Thepresence of the local block signal indicates the communication statebetween node processor 72 and CCPU 24. If the local block signal ispresent in signals received from CCPU 24, Node processor uses CCPU 24control and protective actions to determine breaker control actions. Ifthe local block signal is not present, node processor 72 uses localcontrol and protective actions to determine breaker control actions.Node processor 72 transmits breaker control action through actuationrelay module 88, actuation power module 90, and the standard wiringharness.

[0029] Data received from A/D converter 78 and status input 86 by nodeprocessor 72 are transmitted to CCPU 24 via node electronics unit 20,and digital network 22. The data sent is to CCPU 24 is pre-processeddata from node processor 72, in that, the data sent to CCPU 24 is sentin its raw form, before processing by node processor 72 takes place. Thedata transmitted to CCPU 24 via node electronics unit 20 is processed byCCPU 24, which transmits a signal to node electronics unit 20 viadigital network 22. In the exemplary embodiment, node electronics unit20 actuates circuit breaker 16 in response to the signal received fromCCPU 24. In one embodiment, circuit breaker 16 is actuated in responseto commands sent only by CCPU 24, i.e., circuit breaker 16 is notcontrolled locally, but rather is operated remotely from CCPU 24 basedon inputs received from current transformer 82, potential transformer84, and status inputs 86 received from node electronics unit 20 overnetwork 22.

[0030]FIG. 5 is an exemplary schematic illustration of circuit breaker16 that is electrically coupled to node electronics unit 20. In theexemplary embodiment, circuit breaker 16 includes a switch assembly thatincludes movable and/or stationary contacts, an arc suppression means,and a tripping and operating mechanism. Circuit breaker 16 auxiliariesinclude only a trip coil 100, a close coil 102, an auxiliary switch 104,a spring charge switch 106, and a motor 108. Circuit breaker 16 does notinclude a trip unit. Auxiliary switches and sensors are coupled to nodeelectronics unit 20 through a standard wiring harness 110, which mayinclude both copper wiring and communications conduits. Current sensor82, and voltage sensor 84 are coupled to node electronics unit 20through a cable 112 that may include copper wiring and/or communicationsconduits. Circuit breaker 16 is a unitary device mounted proximate toCCPU 20, current sensor 82, and voltage sensor 84.

[0031] In use, actuation signals from node electronics unit 20 aretransmitted to circuit breaker 16 to actuate a plurality of functions incircuit breaker 16, such as, but not limited to, operating a trip coil100, operating a close coil 102, and affecting a circuit breaker lockoutfeature. An auxiliary switch 104 and spring charge switch 106 provide astatus indication of circuit breaker parameters to node electronics unit20. Motor 108 is configured to recharge a close spring (not shown) aftercircuit breaker 16 closes. To close circuit breaker 16, a close coil 102is energized by a close signal from actuation power module 90. Closecoil 102 actuates a closing mechanism (not shown) that couples at leastone movable electrical contact (not shown) to a corresponding fixedelectrical contact (not shown). The closing mechanism of circuit breaker16 latches in a closed position such that when close coil 102 isde-energized, circuit breaker 16 remains closed. When breaker 16 closes,an “a” contact of auxiliary switch 104 also closes and a “b” contact ofauxiliary switch 104 opens. The position of the “a” and “b” contacts issensed by node electronics unit 20. To open circuit breaker 16, nodeelectronics unit 20 energizes trip coil (TC) 100. TC 100 acts directlyon circuit breaker 16 to release the latching mechanism that holdscircuit breaker 16 closed. When the latching mechanism is released,circuit breaker 16 will open, opening the “a” contact and closing the“b” contact of auxiliary switch 104. Trip coil 100 is then de-energizedby node electronics unit 20. After breaker 16 opens, with the closespring recharged by motor 108, circuit breaker 16 is prepared for a nextoperating cycle. In the exemplary embodiment, each node electronics unit20 is coupled to circuit breaker 16 in a one-to-one correspondence. Forexample, each node electronics unit 20 communicates directly with onlyone circuit breaker 16. In an alternative embodiment, node electronicsunit 20 may communicate with a plurality of circuit breakers 16.

[0032]FIG. 6 is an expanded schematic block diagram of an exemplary nodeelectronics unit 20 shown in FIG. 4. Node electronics unit 20 functionsto perform at least the following functions, sample a current flowthrough circuit breaker 16 and/or a voltage across circuit breaker 16and synchronized to within about 10 microseconds of the sampling of allother node electronics units 20, transmit current and/or voltagemeasurements and node electronics unit 20 and/or circuit breaker 16state to central control processing unit (CCPU) 24 through network 22,and receive and decode commands issued by CCPU 24 communicativelycoupled through network 22. These functions need to occur withsufficient temporal speed such that all power distribution system 10control latency requirements are met. For example, in an instantaneousovercurrent (IOC) event at one of circuit breaker 16, a TRIP commandshould be issued for the affected circuit breaker and executed by theassociated node electronics unit 20 within 2.6 milliseconds of the onsetof IOC.

[0033] Components of node electronics unit 20 that are identical to nodeelectronics unit 20 components shown n FIG. 4 are shown in FIG. 6 usingthe same reference numerals used in FIG. 4. Accordingly, nodeelectronics unit 20 includes node processor 72, sample and hold A/Dconverter 76, communication interface 70, and network 22. Additionally,node electronics unit 20 includes an execution timer 602, externalinterrupt channel 604 and internal interrupt channel 606. Sample andhold A/D converter 76 includes a data input from signal conditioner 78(not shown) via an input channel 608. Sample and hold A/D converter 76also includes communications paths 610 and 612 to node processor 72 fortransmitting a sample command 610 and transmitting digital sampled data612

[0034] Node processor 72 includes an interrupt handler 614 whichreceives interrupt requests from external components via channel 604,internal components via channel 606, execution timer 602, andcommunications interface 70. Interrupt handler 614 also servicesinterrupt requests generated onboard processor 72. Node processor 72includes a polling subroutine 616 operating in a background environment.Polling subroutine 616 executes when interrupt handler 614 is notservicing interrupts, thus utilizing node processor 72 resources onlywhen the resources are not needed to service higher priority requests.Polling subroutine 616 polls a plurality of process execution flags 618that are set by other processes executing in processor 72. A highpriority interrupt may start a process that needs lower priorityprocesses to execute, and may set a process execution flag to requestservice for the process. Likewise, lower priority processes may spawnother processes by setting an execution flag for that process. Processor72 is programmed to include functions such as an integrator, adifferentiator, an amplifier, a comparator, a voltage reference and acurrent reference for processor operation during periods of powerinterruption or poor power quality supplied to node electronics unit 20,when processor 72 may be operating from a self-powered functionprocessing analog input signals.

[0035] In operation, node electronics unit 20 utilizes a softwarearchitecture that enables real-time, synchronized monitoring and controlof node electronics unit 20 and circuit breaker 16. In this softwarearchitecture, node processes are triggered by external or internalinterrupts, or through background polling of process execution flags.High priority process components, for example components that needimmediate processing for the system to achieve latency goals, areexecuted within interrupt handler 614. If follow-on low priorityprocesses are to occur, a flag 618 is set for the follow-on process.When interrupt handler 616 is not executing, a low priority polling loopis running, checking the status of process flags 618. If a process'sflag is set, its process flag is cleared and the process is executed. Asdescribed above, this process may enable the execution of furtherfollow-on processes by setting their process flags.

[0036] In the exemplary embodiment, high priority processes forexecution may include recording the local time of an arriving packet,which is triggered by an interrupt from communications interface 70,initiation of data sampling by sample and hold A/D converter 76,execution timer reset, which is triggered by a timer expirationinterrupt, and enabling data sample collection, which is triggered by adata ready interrupt from A/D converter 76. Follow-on processes that maybe initiated by the high-priority processes may include low priorityexecution of command message decoding and execution, synchronizationprocesses as needed, for example, when a particular command message isreceived, low priority evaluation of communication channel health,reading of a set of data samples from the A/D converter, and loading theset of data samples into a data packet. The data packet is transmittedto CCPU 24 when all of the data sample fields of the data packet's havebeen filled with new data (since the previous packet transmission).

[0037] The software architecture of node electronics unit 20 enablesreal-time, synchronized monitoring and control of node electronics unit20, such as synchronized sampling and transmission of circuit breaker 16currents and voltages to CCPU 24, and real-time reception and executionof commands issued by CCPU 24. The software architecture also providesfor division of processes into high priority (i.e. immediate—interruptdriven) and low priority categories, execution of high priority tasksthat are important for real-time, synchronized node operation, and useof flags and polling to enable execution of lower priority tasks. Highpriority tasks, which are triggered by interrupts may include recordingthe local time of an arriving message packet, initiating A/D converter76 data acquisition, resetting timer 602, and enabling data samplecollection. Lower priority tasks, which are triggered through thepolling of flags set by other processes may include decoding ofreceived, messages and execution of received message commands,evaluation of communication channel health, reading of data samples fromA/D converter 76, and transmission of node electronics unit informationto CCPU 24.

[0038]FIG. 7 is a flow chart illustrating an exemplary method 700 foroperating the node electronics unit shown in FIG. 6. In the exemplaryembodiment, the node electronics unit is a component of a centrallycontrolled power distribution system wherein the power distributionsystem includes a plurality of circuit breakers that are each coupled toa single node electronics unit. Each node electronics unit includes aplurality of processors and a memory, and is communicatively coupled toat least one CCPU through an associated network. Method 700 includestriggering 702 a first node electronics unit process with a processorinterrupt. High priority processes may originate internal to theprocessor and/or external to the processor. An interrupt handler,executing on each processor services each received interrupt. Aninterrupt may trigger a high priority process such as recording a localtime of an arriving message packet, initiation of an A/D converter datasampling and a timer reset, and enabling data sample collection. Aninterrupt that triggers 702 recording the local time of an arrivingmessage packet is an example of an interrupt from an interrupt sourceexternal to processor. Such an interrupt may originate in communicationsinterface. Triggering an initiation of the A/D converter data samplingand the timer reset is an example of an interrupt from an interruptsource internal to processor such as from a timer expiration interrupt.Additionally, a device such as A/D converter may signal a data readycondition to processor using an interrupt. Node electronics unitprocessor includes a background polling process for processes that arenot high priority processes. A lower priority request triggers 704 asecond node electronics unit process by background polling of aplurality of process execution flags and/or a scheduled processorinterrupt. A device or routine requests servicing of a lower priorityprocess by setting at least one process execution flag, processor pollsthe process execution flags when processor interrupt handler 614 is notexecuting, and triggers a low priority process when a process executionflag is set. A first process initiated by a process execution flag mayspawn another second process such that a follow-on process executionflag is set by the first process to enable execution of a follow-onprocess. In the exemplary embodiment, interrupt handler 614 services theprocessor interrupts. In an alternative embodiment, interrupts arehandled using the processor operating system, and processes arescheduled using the processor operating system.

[0039] Exemplary processes that may be initiated using a processexecution flag include decoding of received messages and executingreceived message commands, evaluating communication channel health,conducting a node electronics unit self-evaluation, reading data samplesfrom a node electronics unit A/D converter, executing local protection,logging diagnostic history, logging event history, reading circuitbreaker status, reading node identification, determining identificationof systems units, updating system unit identification, executing asynchronization routine, adaptively modifying node electronics unitparameters and process execution, and transmitting node electronics unitinformation to the CCPUs.

[0040] Node electronics unit parameters may include a local protectionfunction parameter, a communication parameter, a sampling parameter, adiagnostic parameter, and a calibration parameter. Node electronics unitprocess execution may include a condition for triggering a process,adding a new trigger, replacing an existing trigger, replacing anexisting process with an alternate process, adding a new process,removing an existing process. When replacing an existing process with analternate process, the existing process may be replaced with analternate process that is resident in the node and the alternate processmay be identified by a process description received from a remote sourcesuch as a remote processor, a remote controller, a manual entry, anexternal process server, an external code server, a storage media, andthe a process description may include a binary, executable, compilablesource code, interpretable source code, or references to resident codeblocks.

[0041] Node electronics unit parameters and process execution may beadaptively modified based on system resources, a communication networknoise level, a data signal-to-noise ratio, a change in a number ofnetwork nodes, a communication channel utilization, a change ofauthorization of parameters, service requested data, and a changecommand received from at least one of a remote controller and anexternal processor. The node electronics unit senses parametersassociated with potential system problems and routinely performs systemtroubleshooting and diagnostic self checks to facilitate maintainingoptimal system operation during periods of less than optimal systemconditions.

[0042] Node electronics unit parameters and process execution may beadaptively modified based on service requested data that may includesystem status data, local status data, local health data, communicationnetwork data, data signal-to-noise ratio, event history, and errorhistory.

[0043] To facilitate efficient operation during foreseeable operatingconditions at least one of the plurality of processors may be configuredto operate at a first power consumption, which would be the powerconsumption level during a normal operating period, and also configuredto operate at a second, reduced power consumption, which would occurduring periods of a loss of normal power to the node electronics unit asmay occur during a fault in the power supply. Additionally, a processormay be programmed to operate as a primary processor and a secondprocessor may be programmed to operate as a secondary processor. Theprimary processor is operable to perform the functions of a processor ina normal mode and the secondary processor is operable in a sleep modeand may be self powered. The secondary processor may remain in sleepmode until activated by an external signal, such as a loss of power tothe node electronics unit or may “wake-up” periodically, based on aninternal timer, to determine the status of the node electronics unit andthen reenter sleep mode. The secondary processor may be configured tooperate with ultra-low power, at very high processor speed, and becapable of a short power-up or initialization time. During periods whenthe node electronics unit is supplied with normal power, the secondaryprocessor may communicate secondary processor status, secondaryprocessor health, and secondary processor events to the primaryprocessor, and may receive commands, parameters, status information, andhealth information from the primary processor.

[0044] In the exemplary embodiment, at least one processor is programmedto execute a watchdog timer function for monitoring the health of theother processors. Processor generates a first “heartbeat” signal andtransmits the heartbeat signal to each other processor or apredetermined number of the other processors. Each processor thatreceives the first heartbeat signal and is healthy, responds with asecond heartbeat signal, which each processor transmits to the sendingprocessor. The sending processor is programmed to determine the healthof the other processors based on heartbeat signals received and thewatchdog timer.

[0045] A processor may be programmed to execute a power supplymonitoring function that includes logging power supply events,determining a health of the power supply, and transmitting commandsbased on the determined health, for example, writing power supply statusdata to a nonvolatile memory, executing a reduced instruction set toconserve power, and transferring processing control to a processoroperating at reduced power consumption. The processor may further beprogrammed to execute a backup protection function when operating atreduced power consumption. During reduced power consumption theprocessor may operate only selected high priority functions using areduced instruction set and/or reduced clock speed. In the exemplaryembodiment, the processor executes the backup protection function usinganalog signal processing and bypassing the A/D converter to conservepower. As described above, the processor includes functionality thatincludes an integrator, a differentiator, an amplifier, a comparator, avoltage reference and a current reference for processing the analoginput signals. The processor receives analog signals from a source, suchas, a current transformer, potential transformer, and/or a status inputdevice, and processes the analog signal using the integrator, thedifferentiator, the amplifier, the comparator, the voltage reference andthe current reference.

[0046] The above-described power distribution system node electronicsunit software architecture is cost-effective and highly reliable. Thesoftware architecture enables real-time, synchronized monitoring andcontrol of all node electronics units operating on the powerdistribution system. The software architecture also provides fordivision of processes into high priority and low priority categories,such that node resources are used efficiently and system latency timesmay be maintained below predetermined goals. Accordingly, the powerdistribution system node electronics unit software architecturefacilitates protection and monitoring of the power distribution systemin a cost-effective and reliable manner.

[0047] Exemplary embodiments of power distribution system nodeelectronics unit components are described above in detail. Thecomponents are not limited to the specific embodiments described herein,but rather, components of each system may be utilized independently andseparately from other components described herein. Each powerdistribution system node electronics unit component can also be used incombination with other power distribution system components.

[0048] While the invention has been described in terms of variousspecific embodiments, those skilled in the art will recognize that theinvention can be practiced with modification within the spirit and scopeof the claims.

What is claimed is:
 1. A method for operating a power distributionsystem comprising: interrupting a first process of a node electronicsunit with a processor interrupt signal; and initiating a second processof said node electronics unit with a polling process.
 2. A method inaccordance with claim 1 wherein interrupting of said first processcomprises: interrupting said first process with at least one signalselected from the group consisting of: an internal processor interruptsignal and an external processor interrupt signal; and servicing theprocessor interrupt signal with an interrupt handler executing on thenode electronics unit.
 3. A method in accordance with claim 2 whereininterrupting said first process comprises triggering at least one ofrecording a local time of an arriving message packet, initiating an A/Dconverter data sampling and a timer reset, and enabling data samplecollection.
 4. A method in accordance with claim 3 wherein recordingsaid local time comprises receiving an arriving message packet from acommunication interface interrupt.
 5. A method in accordance with claim3 wherein initiating said A/D converter data sampling and timer resetcomprises receiving a timer expiration interrupt.
 6. A method inaccordance with claim 3 wherein enabling said data sample collectioncomprises receiving an A/D converter data ready interrupt.
 7. A methodin accordance with claim 1 wherein initiating said second processcomprises: setting at least one process execution flag; polling said atleast one process execution flag when a processor interrupt handler isnot executing; and triggering a low priority process with said at leastone process execution flag.
 8. A method in accordance with claim 1further comprising setting a follow-on process execution flag to enableexecution of a follow-on process.
 9. A method in accordance with claim 1further comprising: handling interrupts using an operating system; andscheduling processes using the operating system.
 10. A method inaccordance with claim 1 wherein initiating a second process of said nodeelectronics unit with a polling process further comprises triggering atleast one process selected from the group consisting of decoding ofreceived messages and executing received message commands, evaluatingcommunication channel health, conducting a node electronics unitself-evaluation, reading data samples from a node electronics unit A/Dconverter, executing local protection, logging diagnostic history,logging event history, reading circuit breaker status, reading nodeidentification, determining identification of systems units, updatingsystem unit identification, executing a synchronization routine,adaptively modifying node electronics unit parameters and processexecution, and transmitting node electronics unit information to thecentral control processing unit.
 11. A method in accordance with claim10 wherein said process of adaptively modifying node electronics unitparameters and process execution further comprises adaptively modifyingnode electronics unit parameters and process execution based on at leastone selected from the groups consisting of: system resources, acommunication network noise level, a data signal-to-noise ratio, achange in a number of network nodes, a communication channelutilization, a change of authorization of parameters, service requesteddata, and a change command received from at least one of a remotecontroller and an external processor.
 12. A method in accordance withclaim 11 wherein adaptively modifying node electronics unit parametersand process execution based on service requested data further comprisesadaptively modifying node electronics unit parameters and processexecution based on at least one selected from the group consisting of:system status data, local status data, local health data, communicationnetwork data, a data signal-to-noise ratio, event history, and errorhistory.
 13. A method in accordance with claim 10 wherein adaptivelymodifying node electronics unit parameters further comprises adaptivelymodifying at least one selected from the group consisting of: a localprotection function parameter, a communication parameter, a samplingparameter, a diagnostic parameter, and a calibration parameter.
 14. Amethod in accordance with claim 10 wherein adaptively modifying nodeelectronics unit process execution further comprises at least oneselected from the groups consisting of: adaptively modifying a conditionfor triggering a process, adding a new trigger, replacing an existingtrigger, replacing an existing process with an alternate process, addinga new process, removing an existing process.
 15. A method in accordancewith claim 14 replacing an existing process with an alternate processfurther comprises replacing an existing process with a process residentin the node and a process description received from a remote sourcewherein a remote source includes at least one selected from the groupsconsisting of a remote processor, a remote controller, a manual entry,an external process server, an external code server, a storage media,and wherein a process description includes at least one of binaryexecutable, compilable source code, interpretable source code, andreferences to resident code blocks.
 16. A method in accordance withclaim 1 wherein at least one of the plurality of processors isconfigured to operate at a first power consumption and to operate at asecond, reduced power consumption wherein the power consumption of eachconfigured processor operating at the first power consumption is greaterthan the power consumption of each configured processor operating at thesecond power consumption, and wherein the method further comprisesoperating at least one processor at a reduced power consumption.
 17. Amethod in accordance with claim 16 wherein a first processor isprogrammed to operate as a primary processor and a second processor isprogrammed to operate as a secondary processor and wherein the methodfurther comprises: communicating a status of the secondary processor tothe primary processor if power to the node electronics unit isavailable; receiving at least one of commands, parameters, statusinformation, and health information from the primary processor; andreporting at least one of secondary processor status, a secondaryprocessor health, and a secondary processor event to the primaryprocessor.
 18. A method in accordance with claim 16 wherein at least oneprocessor is programmed to execute a watchdog timer function, the methodfurther comprising: generating a first signal; transmitting the firstsignal to at least one other processor; receiving a second signal fromanother processor; and determining a health of the other processor basedon the second signal.
 19. A method in accordance with claim 16 whereinat least one processor is programmed to execute a power supplymonitoring function and wherein the method further comprises: loggingpower supply events; determining a health of the power supply; andtransmitting commands based on the determined health.
 20. A method inaccordance with claim 19 further comprising: writing power supply statusdata to a nonvolatile memory; executing a reduced instruction set toconserve power; and transferring processing control to a processoroperating at reduced power consumption.
 21. A method in accordance withclaim 16 wherein the at least one processor is further programmed toexecute a backup protection function when operating at reduced powerconsumption and wherein the method further comprises executing thebackup protection function using analog signal processing.
 22. A methodin accordance with claim 21 wherein the processor includes anintegrator, a differentiator, an amplifier, a comparator, a voltagereference and a current reference for processing analog input signalsand wherein the method further comprises: receiving an analog signalfrom a source; and processing the analog signal using at least one ofthe integrator, the differentiator, the amplifier, the comparator, thevoltage reference and the current reference.
 23. A system for operatinga power distribution system comprising: means for interrupting a firstprocess of a node electronics unit with a processor interrupt signal;and means for initiating a second process of said node electronics unitwith a polling process.
 24. A system in accordance with claim 23 furthercomprising: means for interrupting said first process with at least onesignal selected from the group consisting of: an internal processorinterrupt signal and an external processor interrupt signal; and meansfor servicing the processor interrupt signal with an interrupt handlerexecuting on the node electronics unit.
 25. A system in accordance withclaim 24 wherein means for interrupting said first process comprisesmeans for triggering at least one of recording a local time of anarriving message packet, initiating an A/D converter data sampling and atimer reset, and enabling data sample collection.
 26. A system inaccordance with claim 25 wherein recording said local time comprisesreceiving an arriving message packet from a communication interfaceinterrupt.
 27. A system in accordance with claim 25 wherein recordingsaid local time comprises receiving an arriving message packet from acommunication interface interrupt.
 28. A system in accordance with claim25 wherein initiating said A/D converter data sampling and timer resetcomprises receiving a timer expiration interrupt.
 29. A system inaccordance with claim 23 means for initiating said second processcomprises: means for setting at least one process execution flag; meansfor polling said at least one process execution flag when a processorinterrupt handler is not executing; and means for triggering a lowpriority process with said at least one process execution flag.
 30. Asystem in accordance with claim 29 further comprising means fortriggering at least one process selected from the group consisting of:decoding of received messages and execution of received messagecommands, evaluation of communication channel health, reading of datasamples from a node electronics unit A/D converter, and transmission ofnode electronics unit information to said central control processingunit.
 31. A system in accordance with claim 23 further comprising meansfor setting a follow-on process execution flag to enable execution of afollow-on process.
 32. A system for operating power distribution systemcomprising: interrupting a first process of a node electronics unit witha processor interrupt signal; means for servicing the processorinterrupt signal with an interrupt handler executing on the nodeelectronics unit and initiating a second process of said nodeelectronics unit with a polling process.